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| FM3104/16/64/256 Integrated Processor Companion with Memory Features High Integration Device Replaces Multiple Parts * Serial Nonvolatile Memory * Real-time Clock (RTC) * Low Voltage Reset * Watchdog Timer * Early Power-Fail Warning/NMI * Two 16-bit Event Counters * Serial Number with Write-lock for Security Ferroelectric Nonvolatile RAM * 4Kb, 16Kb, 64Kb, and 256Kb versions * Unlimited Read/Write Endurance * 10 year Data Retention * NoDelayTM Writes Real-time Clock/Calendar * Backup Current under 1 A * Seconds through Centuries in BCD format * Tracks Leap Years through 2099 * Uses Standard 32.768 kHz Crystal (6pF) * Software Calibration * Supports Battery or Capacitor Backup Processor Companion * Active-low Reset Output for VDD and Watchdog * Programmable VDD Reset Trip Point * Manual Reset Filtered and Debounced * Programmable Watchdog Timer * Dual Battery-backed Event Counter Tracks System Intrusions or other Events * Comparator for Early Power-Fail Interrupt * 64-bit Programmable Serial Number with Lock Fast Two-wire Serial Interface * Up to 1 MHz Maximum Bus Frequency * Supports Legacy Timing for 100 kHz & 400 kHz * Device Select Pins for up to 4 Memory Devices * RTC, Supervisor Controlled via 2-wire Interface Easy to Use Configurations * Operates from 2.7 to 5.5V * Small Footprint 14-pin "Green" SOIC (-G) * Low Operating Current * -40C to +85C Operation Description The FM31xx is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, realtime clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interrupt or other purpose. The family operates from 2.7 to 5.5V. Each FM31xx provides nonvolatile RAM available in sizes including 4Kb, 16Kb, 64Kb, and 256Kb versions. Fast write speed and unlimited endurance allow the memory to serve as extra RAM or conventional nonvolatile storage. This memory is truly nonvolatile rather than battery backed. The real-time clock (RTC) provides time and date information in BCD format. It can be permanently powered from external backup voltage source, either a battery or a capacitor. The timekeeper uses a common external 32.768 kHz crystal and provides a calibration mode that allows software adjustment of timekeeping accuracy. This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron's internal qualification testing and has reached production status. Rev. 3.2 July 2010 The processor companion includes commonly needed CPU support functions. Supervisory functions include a reset output signal controlled by either a low VDD condition or a watchdog timeout. /RST goes active when VDD drops below a programmable threshold and remains active for 100 ms after VDD rises above the trip point. A programmable watchdog timer runs from 100 ms to 3 seconds. The watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not restarted by the host before the timeout. A flag-bit indicates the source of the reset. A general-purpose comparator compares an external input pin to the onboard 1.2V reference. This is useful for generating a power-fail interrupt (NMI) but can be used for any purpose. The family also includes a programmable 64-bit serial number that can be locked making it unalterable. Additionally it offers a dual battery-backed event counter that tracks the number of rising or falling edges detected on dedicated input pins. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Page 1 of 25 FM3104/16/64/256 Pin Configuration CNT1 CNT2 A0 A1 CAL/PFO RST VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD SCL SDA X2 X1 PFI VBAK Pin Name CNT1, CNT2 A0, A1 CAL/PFO /RST PFI X1, X2 SDA SCL VBAK VDD VSS Function Event Counter Inputs Device Select inputs Clock Calibration and Early Power-Fail Output Reset Input/Output Early Power-fail Input Crystal Connections Serial Data Serial Clock Battery-Backup Supply Supply Voltage Ground Ordering Information Base Configuration FM31256 FM3164 FM3116 FM3104 Memory Size 256Kb 64Kb 16Kb 4Kb Operating Voltage 2.7-5.5V 2.7-5.5V 2.7-5.5V 2.7-5.5V Reset Threshold 2.6V, 2.9, 3.9, 4.4V 2.6V, 2.9, 3.9, 4.4V 2.6V, 2.9, 3.9, 4.4V 2.6V, 2.9, 3.9, 4.4V Ordering Part Number FM31256-G FM3164-G FM3116-G FM3104-G Other memory configurations may be available. Please contact the factory for more information. Rev. 3.2 July 2010 Page 2 of 25 FM3104/16/64/256 A1, A0 SCL SDA 2-Wire Interface LockOut FRAM Array LockOut RST Watchdog LV Detect Special Function Registers S/N RTC Cal. RTC Registers X1 PFI + CAL/PFO 2.5V 1.2V RTC X2 512Hz Event Counters CNT1 CNT2 + VDD Switched Power VBAK Nonvolatile Battery Backed Figure 1. Block Diagram Pin Descriptions Pin Name A0, A1 CNT1, CNT2 CAL/PFO X1, X2 /RST SDA Type Input Input Output I/O I/O I/O Pin Description Device select inputs are used to address multiple memories on a serial bus. To select the device the address value on the two pins must match the corresponding bits contained in the device address. The device select pins are pulled down internally. Event Counter Inputs: These battery-backed inputs increment counters when an edge is detected on the corresponding CNT pin. The polarity is programmable. These pins should not be left floating. Tie to ground if pins are not used. In calibration mode, this pin supplies a 512 Hz square-wave output for clock calibration. In normal operation, this is the early power-fail output. 32.768 kHz crystal connection. When using an external oscillator, apply the clock to X1 and a DC mid-level to X2 (see Crystal Oscillator section for suggestions). Active low reset output with weak pull-up. Also input for manual reset. Serial Data & Address: This is a bi-directional line for the two-wire interface. It is open-drain and is intended to be wire-OR'd with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. A pull-up resistor is required. Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the part on the falling edge, and in on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. Early Power-fail Input: Typically connected to an unregulated power supply to detect an early power failure. This pin should not be left floating. Backup supply voltage: A 3V battery or a large value capacitor. If VDD<3.6V and no backup supply is used, this pin should be tied to VDD. If VDD>3.6V and no backup supply is used, this pin should be left floating and the VBC bit should be set. Supply Voltage Ground SCL PFI VBAK VDD VSS Input Input Supply Supply Supply Rev. 3.2 July 2010 Page 3 of 25 FM3104/16/64/256 Overview The FM31xx family combines a serial nonvolatile RAM with a real-time clock (RTC) and a processor companion. The companion is a highly integrated peripheral including a processor supervisor, a comparator used for early power-fail warning, nonvolatile event counters, and a 64-bit serial number. The FM31xx integrates these complementary but distinct functions that share a common interface in a single package. Although monolithic, the product is organized as two logical devices, the FRAM memory and the RTC/companion. From the system perspective they appear to be two separate devices with unique IDs on the serial bus. The memory is organized as a stand-alone 2-wire nonvolatile memory with a standard device ID value. The real-time clock and supervisor functions are accessed with a separate 2-wire device ID. This allows clock/calendar data to be read while maintaining the most recently used memory address. The clock and supervisor functions are controlled by 25 special function registers. The RTC and event counter circuits are maintained by the power source on the VBAK pin, allowing them to operate from battery or backup capacitor power when VDD drops below an internally set threshold. Each functional block is described below. protected addresses. The special function registers containing these bits are described in detail below. Write protect addresses None Bottom 1/4 Bottom 1/2 Full array WP1 0 0 1 1 WP0 0 1 0 1 Processor Companion In addition to nonvolatile RAM, the FM31xx family incorporates a highly integrated processor companion. It includes a low voltage reset, a programmable watchdog timer, battery-backed event counters, a comparator for early power-fail detection or other purposes, and a 64-bit serial number. Processor Supervisor Supervisors provide a host processor two basic functions: detection of power supply fault conditions and a watchdog timer to escape a software lockup condition. All FM31xx devices have a reset pin (/RST) to drive the processor reset input during power faults (and power-up) and software lockups. It is an open drain output with a weak internal pull-up to VDD. This allows other reset sources to be wireOR'd to the /RST pin. When VDD is above the programmed trip point, /RST output is pulled weakly to VDD. If VDD drops below the reset trip point voltage level (VTP) the /RST pin will be driven low. It will remain low until VDD falls too low for circuit operation which is the VRST level. When VDD rises again above VTP, /RST will continue to drive low for at least 100 ms (tRPU) to ensure a robust system reset at a reliable VDD level. After tRPU has been met, the /RST pin will return to the weak high state. While /RST is asserted, serial bus activity is locked out even if a transaction occurred as VDD dropped below VTP. A memory operation started while VDD is above VTP will be completed internally. Figure 2 below illustrates the reset operation in response to the VDD voltage. VDD VTP tRPU Memory Operation The FM31xx is a family of products available in different memory sizes including 4Kb, 16Kb, 64Kb, and 256Kb. The family is software compatible, all versions use consistent two-byte addressing for the memory device. This makes the lowest density device different from its stand-alone memory counterparts but makes them compatible within the entire family. Memory is organized in bytes, for example the 4Kb memory is 512 x 8 and the 256Kb memory is 32,768 x 8. The memory is based on FRAM technology. Therefore it can be treated as RAM and is read or written at the speed of the two-wire bus with no delays for write operations. It also offers effectively unlimited write endurance unlike other nonvolatile memory technologies. The 2-wire interface protocol is described further on page 13. The memory array can be write-protected by software. Two bits in the processor companion area (WP0, WP1 in register 0Bh) control the protection setting as shown in the following table. Based on the setting, the protected addresses cannot be written and the 2-wire interface will not acknowledge any data to Rev. 3.2 July 2010 RST Figure 2. Low Voltage Reset The bits VTP1 and VTP0 control the trip point of the low voltage detect circuit. They are located in register 0Bh, bits 1 and 0. Page 4 of 25 FM3104/16/64/256 VTP 2.6V 2.9V 3.9V 4.4V VTP1 0 0 1 1 VTP0 0 1 0 1 Manual Reset The /RST pin is bi-directional and allows the FM31xx to filter and de-bounce a manual reset switch. The /RST input detects an external low condition and responds by driving the /RST signal low for 100 ms. MCU RST Reset Switch FM31xx The watchdog timer can also be used to assert the reset signal (/RST). The watchdog is a free running programmable timer. The period can be software programmed from 100 ms to 3 seconds in 100 ms increments via a 5-bit nonvolatile register. All programmed settings are minimum values and vary with temperature according to the operating specifications. The watchdog has two additional controls associated with its operation, a watchdog enable bit (WDE) and timer restart bits (WR). Both the enable bit must be set and the watchdog must timeout in order to drive /RST active. If a reset event occurs, the timer will automatically restart on the rising edge of the reset pulse. If WDE=0, the watchdog timer runs but a watchdog fault will not cause /RST to be asserted low. The WTR flag will be set, indicating a watchdog fault. This setting is useful during software development and the developer does not want /RST to drive. Note that setting the maximum timeout setting (11111b) disables the counter to save power. The second control is a nibble that restarts the timer preventing a reset. The timer should be restarted after changing the timeout value. The watchdog timeout value is located in register 0Ah, bits 4-0, and the watchdog enable is bit 7. The watchdog is restarted by writing the pattern 1010b to the lower nibble of register 09h. Writing this pattern will also cause the timer to load new timeout values. Writing other patterns to this address will not affect its operation. Note the watchdog timer is freerunning. Prior to enabling it, users should restart the timer as described above. This assures that the full timeout period will be set immediately after enabling. The watchdog is disabled when VDD is below VTP. The following table summarizes the watchdog bits. A block diagram follows. Watchdog timeout Watchdog enable Watchdog restart WDT4-0 WDE WR3-0 0Ah, bits 4-0 0Ah, bit 7 09h, bits 3-0 Switch Behavior RST FM31xx drives 100 ms (min.) Figure 4. Manual Reset Note that an internal weak pull-up on /RST eliminates the need for additional external components. Reset Flags In case of a reset condition, a flag will be set to indicate the source of the reset. A low VDD reset is indicated by the POR flag, register 09h bit 6. A watchdog reset is indicated by the WTR flag, register 09h bit 7. Note that the flags are internally set in response to reset sources, but they must be cleared by the user. When the register is read, it is possible that both flags are set if both have occurred since the user last cleared them. Early Power Fail Comparator An early power fail warning can be provided to the processor well before VDD drops out of spec. The comparator is used to create a power fail interrupt (NMI). This can be accomplished by connecting the PFI pin to the unregulated power supply via a resistor divider. An application circuit is shown below. Regulator VDD Timebase 100 ms clock WR3-0 = 1010b to restart Counter Watchdog timeout /RST To MCU CAL/PFO NMI input FM31xx PFI + - 1.2V ref WDE Figure 3. Watchdog Timer Rev. 3.2 July 2010 Figure 5. Comparator as Early Power-Fail Warning Page 5 of 25 FM3104/16/64/256 The voltage on the PFI input pin is compared to an onboard 1.2V reference. When the PFI input voltage drops below this threshold, the comparator will drive the CAL/PFO pin to a low state. The comparator has 100 mV (max) of hysteresis to reduce noise sensitivity, only for a rising PFI signal. For a falling PFI edge, there is no hysteresis. The comparator is a general purpose device and its application is not limited to the NMI function. The comparator is not integrated into the special function registers except as it shares its output pin with the CAL output. When the RTC calibration mode is invoked by setting the CAL bit (register 00h, bit 2), the CAL/PFO output pin will be driven with a 512 Hz square wave and the comparator will be ignored. Since most users only invoke the calibration mode during production, this should have no impact on system operations using the comparator. Note: The maximum voltage on the comparator input PFI is limited to 3.75V under normal operating conditions. The control bits for event counting are located in register 0Ch. Counter 1 Polarity is bit C1P, bit 0; Counter 2 Polarity is C2P, bit 1; the Cascade Control is CC, bit 2; and the Read Counter bit is RC bit 3. The polarity bits must be set prior to setting the counter value(s). If a polarity bit is changed, the counter may inadvertently increment. If the counter pins are not being used, tie them to ground. Serial Number A memory location to write a 64-bit serial number is provided. It is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. The 8 bytes of data and the lock bit are all accessed via the device ID for the processor companion. Therefore the serial number area is separate and distinct from the memory array. The serial number registers can be written an unlimited number of times, so these locations are general purpose memory. However once the lock bit is set the values cannot be altered and the lock cannot be removed. Once locked the serial number registers can still be read by the system. The serial number is located in registers 11h to 18h. The lock bit is SNL, register 0Bh bit 7. Setting the SNL bit to a 1 disables writes to the serial number registers, and the SNL bit cannot be cleared. Event Counter The FM31xx offers the user two battery-backed event counters. Input pins CNT1 and CNT2 are programmable edge detectors. Each clocks a 16-bit counter. When an edge occurs, the counters will increment their respective registers. Counter 1 is located in registers 0Dh and 0Eh, Counter 2 is located in registers 0Fh and 10h. These register values can be read anytime VDD is above VTP, and they will be incremented as long as a valid VBAK power source is provided. To read, set the RC bit register 0Ch bit 3 to 1. This takes a snapshot of all four counter bytes allowing a stable value even if a count occurs during the read. The registers can be written by software allowing the counters to be cleared or initialized by the system. Counts are blocked during a write operation. The two counters can be cascaded to create a single 32-bit counter by setting the CC control bit (register 0Ch). When cascaded, the CNT1 input will cause the counter to increment. CNT2 is not used in this mode. C1P Real-Time Clock Operation The real-time clock (RTC) is a timekeeping device that can be battery or capacitor backed for permanently-powered operation. It offers a software calibration feature that allows high accuracy. The RTC consists of an oscillator, clock divider, and a register system for user access. It divides down the 32.768 kHz time-base and provides a minimum resolution of seconds (1Hz). Static registers provide the user with read/write access to the time values. It includes registers for seconds, minutes, hours, dayof-the-week, date, months, and years. A block diagram (Figure 7) illustrates the RTC function. The user registers are synchronized with the timekeeper core using R and W bits in register 00h described below. Changing the R bit from 0 to 1 transfers timekeeping information from the core into holding registers that can be read by the user. If a timekeeper update is pending when R is set, then the core will be updated prior to loading the user registers. The registers are frozen and will not be updated again until the R bit is cleared to 0. R is used for reading the time. Setting the W bit to 1 locks the user registers. Clearing it to 0 causes the values in the user registers Page 6 of 25 CNT1 C2P 16-bit Counter CNT2 CC 16-bit Counter Figure 6. Event Counter Rev. 3.2 July 2010 FM3104/16/64/256 to be loaded into the timekeeper core. W is used for writing new time values. Users should be certain not to load invalid values, such as FFh, to the timekeeping registers. Updates to the timekeeping core occur continuously except when locked. Backup Power The real-time clock/calendar is intended to be permanently powered. When the primary system power fails, the voltage on the VDD pin will drop. When VDD is less 2.5V the RTC (and event counters) will switch to the backup power supply on VBAK. The clock operates at extremely low current in order to maximize battery or capacitor life. However, an advantage of combining a clock function with FRAM memory is that data is not lost regardless of the backup power source. Trickle Charger To facilitate capacitor backup the VBAK pin can optionally provide a trickle charge current. When the VBC bit, register 0Bh bit 2, is set to 1 the VBAK pin will source approximately 15 A until VBAK reaches VDD or 3.75V whichever is less. In 3V systems, this charges the capacitor to VDD without an external diode and resistor charger. In 5V systems, it provides the same convenience and also prevents the user from exceeding the VBAK maximum voltage specification. In the case where no battery is used, the VBAK pin should be tied according to the following conditions: * For 3.3V systems, VBAK should be tied to VDD. This assumes VDD does not exceed 3.75V. * For 5V systems, attach a 1 F capacitor to VBAK and turn the trickle charger on. The VBAK pin will charge to the internal backup voltage which regulates itself to about 3.6V. VBAK should not be tied to 5V since the VBAK (max) specification will be exceeded. A 1 F capacitor will keep the companion functions working for about 1.5 second. Although VBAK may be connected to VSS, this is not recommended if the companion is used. None of the companion functions will operate below about 2.5V. Note: systems using lithium batteries should clear the VBC bit to 0 to prevent battery charging. The VBAK circuitry includes an internal 1 K series resistor as a safety element. /OSCEN 32.768 kHz crystal Clock Divider 512 Hz W Oscillator 1 Hz Update Logic CF Years 8 bits Months 5 bits Date 6 bits Days 3 bits Hours 6 bits Minutes 7 bits Seconds 7 bits User Interface Registers R Figure 7. Real-Time Clock Core Block Diagram Calibration When the CAL bit in a register 00h is set to 1, the clock enters calibration mode. In calibration mode, the CAL/PFO output pin is dedicated to the calibration function and the power fail output is temporarily unavailable. Calibration operates by applying a digital correction to the counter based on the frequency error. In this mode, the CAL/PFO pin is driven with a 512 Hz (nominal) square wave. Any measured deviation from 512 Hz translates into a timekeeping error. The user converts the measured Rev. 3.2 July 2010 error in ppm and writes the appropriate correction value to the calibration register. The correction factors are listed in the table below. Positive ppm errors require a negative adjustment that removes pulses. Negative ppm errors require a positive correction that adds pulses. Positive ppm adjustments have the CALS (sign) bit set to 1, where as negative ppm adjustments have CALS = 0. After calibration, the clock will have a maximum error of 2.17 ppm or 0.09 minutes per month at the calibrated temperature. Page 7 of 25 FM3104/16/64/256 The calibration setting is stored in FRAM so is not lost should the backup source fail. It is accessed with bits CAL.4-0 in register 01h. This value only can be written when the CAL bit is set to a 1. To exit the calibration mode, the user must clear the CAL bit to a 0. When the CAL bit is 0, the CAL/PFO pin will revert to the power fail output function. Crystal Oscillator The crystal oscillator is designed to use a 6pF crystal without the need for external components, such as loading capacitors. The FM31xx device has built-in loading capacitors that match the crystal. If a 32.768kHz crystal is not used, an external oscillator may be connected to the FM31xx. Apply the oscillator to the X1 pin. Its high and low voltage levels can be driven rail-to-rail or amplitudes as low as approximately 500mV p-p. To ensure proper operation, a DC bias must be applied to the X2 pin. It should be centered between the high and low levels on the X1 pin. This can be accomplished with a voltage divider. FM31xx X1 X2 Vdd R1 R2 Figure 8. External Oscillator In the example, R1 and R2 are chosen such that the X2 voltage is centered around the X1 oscillator drive levels. If you wish to avoid the DC current, you may choose to drive X1 with an external clock and X2 with an inverted clock using a CMOS inverter. Layout Requirements The X1 and X2 crystal pins employ very high impedance circuits and the oscillator connected to these pins can be upset by noise or extra loading. To reduce RTC clock errors from signal switching noise, a guard ring must be placed around these pads and the guard ring grounded. SDA and SCL traces should be routed away from the X1/X2 pads. The X1 and X2 trace lengths should be less than 5 mm. The use of a ground plane on the backside or inner board layer is preferred. See layout example. Red is the top layer, green is the bottom layer. VDD SCL SDA X2 X1 PFI VBAK VDD SCL SDA X2 X1 PFI VBAK Layout for Surface Mount Crystal (red = top layer, green = bottom layer) Layout for Through Hole Crystal (red = top layer, green = bottom layer) Rev. 3.2 July 2010 Page 8 of 25 FM3104/16/64/256 Calibration Adjustments Positive Calibration for slow clocks: Calibration will achieve 2.17 PPM after calibration Measured Frequency Range Error Range (PPM) Min Max Min Max Program Calibration Register to: 512.0000 511.9989 0 2.17 000000 511.9989 511.9967 2.18 6.51 100001 511.9967 511.9944 6.52 10.85 100010 511.9944 511.9922 10.86 15.19 100011 511.9922 511.9900 15.20 19.53 100100 511.9900 511.9878 19.54 23.87 100101 511.9878 511.9856 23.88 28.21 100110 511.9856 511.9833 28.22 32.55 100111 511.9833 511.9811 32.56 36.89 101000 511.9811 511.9789 36.90 41.23 101001 511.9789 511.9767 41.24 45.57 101010 511.9767 511.9744 45.58 49.91 101011 511.9744 511.9722 49.92 54.25 101100 511.9722 511.9700 54.26 58.59 101101 511.9700 511.9678 58.60 62.93 101110 511.9678 511.9656 62.94 67.27 101111 511.9656 511.9633 67.28 71.61 110000 511.9633 511.9611 71.62 75.95 110001 511.9611 511.9589 75.96 80.29 110010 511.9589 511.9567 80.30 84.63 110011 511.9567 511.9544 84.64 88.97 110100 511.9544 511.9522 88.98 93.31 110101 511.9522 511.9500 93.32 97.65 110110 511.9500 511.9478 97.66 101.99 110111 511.9478 511.9456 102.00 106.33 111000 511.9456 511.9433 106.34 110.67 111001 511.9433 511.9411 110.68 115.01 111010 511.9411 511.9389 115.02 119.35 111011 511.9389 511.9367 119.36 123.69 111100 511.9367 511.9344 123.70 128.03 111101 511.9344 511.9322 128.04 132.37 111110 511.9322 511.9300 132.38 136.71 111111 Negative Calibration for fast clocks: Calibration will achieve 2.17 PPM after calibration Measured Frequency Range Error Range (PPM) Min Max Min Max Program Calibration Register to: 512.0000 512.0011 0 2.17 000000 512.0011 512.0033 2.18 6.51 000001 512.0033 512.0056 6.52 10.85 000010 512.0056 512.0078 10.86 15.19 000011 512.0078 512.0100 15.20 19.53 000100 512.0100 512.0122 19.54 23.87 000101 512.0122 512.0144 23.88 28.21 000110 512.0144 512.0167 28.22 32.55 000111 512.0167 512.0189 32.56 36.89 001000 512.0189 512.0211 36.90 41.23 001001 512.0211 512.0233 41.24 45.57 001010 512.0233 512.0256 45.58 49.91 001011 512.0256 512.0278 49.92 54.25 001100 512.0278 512.0300 54.26 58.59 001101 512.0300 512.0322 58.60 62.93 001110 512.0322 512.0344 62.94 67.27 001111 512.0344 512.0367 67.28 71.61 010000 512.0367 512.0389 71.62 75.95 010001 512.0389 512.0411 75.96 80.29 010010 512.0411 512.0433 80.30 84.63 010011 512.0433 512.0456 84.64 88.97 010100 512.0456 512.0478 88.98 93.31 010101 512.0478 512.0500 93.32 97.65 010110 512.0500 512.0522 97.66 101.99 010111 512.0522 512.0544 102.00 106.33 011000 512.0544 512.0567 106.34 110.67 011001 512.0567 512.0589 110.68 115.01 011010 512.0589 512.0611 115.02 119.35 011011 512.0611 512.0633 119.36 123.69 011100 512.0633 512.0656 123.70 128.03 011101 512.0656 512.0678 128.04 132.37 011110 512.0678 512.0700 132.38 136.71 011111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Rev. 3.2 July 2010 Page 9 of 25 FM3104/16/64/256 Register Map The RTC and processor companion functions are accessed via 25 special function registers mapped to a separate 2wire device ID. The interface protocol is described below. The registers contain timekeeping data, control bits, or information flags. A description of each register follows the summary table below. Register Map Summary Table Nonvolatile = Battery-backed = Address 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h D7 Data D5 D4 D3 Serial Number Byte 7 Serial Number Byte 6 Serial Number Byte 5 Serial Number Byte 4 Serial Number Byte 3 Serial Number Byte 2 Serial Number Byte 1 Serial Number Byte 0 Counter 2 MSB Counter 2 LSB Counter 1 MSB Counter 1 LSB RC WP1 WP0 WDT4 WDT3 POR LB WR3 10 years 0 0 10 mo 0 10 date 0 0 0 0 0 10 hours 10 minutes 10 seconds reserved CALS CAL4 CAL3 CF reserved reserved reserved D6 D2 D1 D0 Function Serial Number 7 Serial Number 6 Serial Number 5 Serial Number 4 Serial Number 3 Serial Number 2 Serial Number 1 Serial Number 0 Event Counter 2 MSB Event Counter 2 LSB Event Counter 1 MSB Event Counter 1 LSB Event Count Control Companion Control Watchdog Control Watchdog Restart/Flags Years Month Date Day Hours Minutes Seconds CAL/Control RTC Control Range FFh FFh FFh FFh FFh FFh FFh FFh FFh FFh FFh FFh SNL WDE WTR 0 0 0 0 0 0 /OSCEN reserved CC C2P VBC VTP1 WDT2 WDT1 WR2 WR1 years months date day hours minutes seconds CAL2 CAL1 CAL W C1P VTP0 WDT0 WR0 00-99 1-12 1-31 1-7 0-23 0-59 0-59 CAL0 R Note: When the device is first powered up and programmed, all registers must be written because the batterybacked register values cannot be guaranteed. The table below shows the default values of the non-volatile registers. All other register values should be treated as unknown. Default Register Values Address 18h 17h 16h 15h 14h 13h 12h 11h 0Bh 0Ah 01h Hex Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F 0x80 Rev. 3.2 July 2010 Page 10 of 25 FM3104/16/64/256 Register Description Address Description 18h Serial Number Byte 7 D7 SN.63 D6 SN.62 D5 SN.61 D4 SN.60 D3 SN.59 D2 SN.58 D1 SN.57 D0 SN.56 Upper byte of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 17h Serial Number Byte 6 D7 SN.55 D6 SN.54 D5 SN.53 D4 SN.52 D3 SN.51 D2 SN.50 D1 SN.49 D0 SN.48 Byte 6 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 16h Serial Number Byte 5 D7 SN.47 D6 SN.46 D5 SN.45 D4 SN.44 D3 SN.43 D2 SN.42 D1 SN.41 D0 SN.40 Byte 5 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 15h Serial Number Byte 4 D7 SN.39 D6 SN.38 D5 SN.37 D4 SN.36 D3 SN.35 D2 SN.34 D1 SN.33 D0 SN.32 Byte 4 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 14h Serial Number Byte 3 D7 SN.31 D6 SN.30 D5 SN.29 D4 SN.28 D3 SN.27 D2 SN.26 D1 SN.25 D0 SN.24 Byte 3 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 13h Serial Number Byte 2 D7 SN.23 D6 SN.22 D5 SN.21 D4 SN.20 D3 SN.19 D2 SN.18 D1 SN.17 D0 SN.16 Byte 2 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 12h Serial Number Byte 1 D7 SN.15 D6 SN.14 D5 SN.13 D4 SN.12 D3 SN.11 D2 SN.10 D1 SN.9 D0 SN.8 Byte 1 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 11h Serial Number Byte 0 D7 SN.7 D6 SN.6 D5 SN.5 D4 SN.4 D3 SN.3 D2 SN.2 D1 SN.1 D0 SN.0 LSB of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 10h Counter 2 MSB D7 C2.15 D6 C2.14 D5 C2.13 D4 C2.12 D3 C2.11 D2 C2.10 D1 C2.9 D0 C2.8 Event Counter 2 MSB. Increments on overflows from Counter 2 LSB. Battery-backed, read/write. 0Fh Counter 2 LSB D7 C2.7 D6 C2.6 D5 C2.5 D4 C2.4 D3 C2.3 D2 C2.2 D1 C2.1 D0 C2.0 Event Counter 2 LSB. Increments on programmed edge event on CNT2 input or overflows from Counter 1 MSB when CC=1. Battery-backed, read/write . 0Eh Counter 1 MSB D7 C1.15 D6 C1.14 D5 C1.13 D4 C1.12 D3 C1.11 D2 C1.10 D1 C1.9 D0 C1.8 Event Counter 1 MSB. Increments on overflows from Counter 1 LSB. Battery-backed, read/write. 0Dh Counter 1 LSB D7 C1.7 D6 C1.6 D5 C1.5 D4 C1.4 D3 C1.3 D2 C1.2 D1 C1.1 D0 C1.0 Event Counter 1 LSB. Increments on programmed edge event on CNT1 input. Battery-backed, read/write. Rev. 3.2 July 2010 Page 11 of 25 FM3104/16/64/256 0Ch Event Counter Control D7 - D6 - D5 - D4 - D3 RC D2 CC D1 C2P D0 C1P RC CC C2P C1P Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the values without missing count events. The RC bit will be automatically cleared. Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is "don't care" when CC=1. Battery-backed, read/write. CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P is "don't care" when CC=1. The value of Event Counter 2 may inadvertently increment if C2P is changed. Battery-backed, read/write. CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. The value of Event Counter 1 may inadvertently increment if C1P is changed. Battery-backed, read/write. 0Bh Companion Control D7 SNL D6 - D5 - D4 WP1 D3 WP0 D2 VBC D1 VTP1 D0 VTP0 SNL WP1-0 Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only. SNL cannot be cleared once set to 1. Nonvolatile, read/write. Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write. Write protect addresses None Bottom 1/4 Bottom 1/2 Full array VBC VTP1-0 WP1 0 0 1 1 WP0 0 1 0 1 VBAK Charger Control. Setting VBC to 1 causes a 15 A trickle charge current to be supplied on VBAK. Clearing VBC to 0 disables the charge current. Nonvolatile, read/write. VTP select. These bits control the reset trip point for the low VDD reset function. Nonvolatile, read/write. 0Ah VTP 2.6V 2.9V 3.9V 4.4V Watchdog Control D7 WDE VTP1 0 0 1 1 D5 - VTP0 0 1 0 1 D4 WDT4 D6 - D3 WDT3 D2 WDT2 D1 WDT1 D0 WDT0 WDE WDT4-0 Watchdog Enable. When WDE=1, a watchdog timer fault will cause the /RST signal to go active. When WDE = 0 the timer runs but has no effect on /RST, however the WTR flag will be set when a fault occurs. Note as the timer is free-running, users should restart the timer using WR3-0 prior to setting WDE=1. This assures a full watchdog timeout interval occurs. Nonvolatile, read/write. Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write. Watchdog timeout Invalid - default 100 ms 100 ms 200 ms 300 ms . . . 2000 ms 2100 ms 2200 ms . . . 2900 ms 3000 ms Disable counter Rev. 3.2 July 2010 WDT4 WDT3 WDT2 WDT1 WDT0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 0 1 0 1 0 1 Page 12 of 25 FM3104/16/64/256 09h Watchdog Restart & Flags D7 WTR D6 POR D5 LB D4 - D3 WR3 D2 WR2 D1 WR1 D0 WR0 WTR POR LB WR3-0 Watchdog Timer Reset Flag: When a watchdog timer fault occurs, the WTR bit will be set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit). Power-on Reset Flag: When the /RST pin is activated by VDD < VTP, the POR bit will be set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit). Low Backup Flag: On power up, if the VBAK source is below the minimum voltage to operate the RTC and event counters, this bit will be set to 1. The user should clear it to 0 when initializing the system. Battery-backed. Read/Write (internally set, user can clear bit). Watchdog Restart: Writing a pattern 1010b to WR3-0 restarts the watchdog timer. The upper nibble contents do not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the timer. This allows users to clear the WTR, POR, and LB flags without affecting the watchdog timer. Battery-backed, Write-only. 08h Timekeeping - Years D7 10 year.3 D6 10 year.2 D5 10 year.1 D4 10 year.0 D3 Year.3 D2 Year.2 D1 Year.1 D0 Year.0 Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Battery-backed, read/write. 07h Timekeeping - Months D7 0 D6 0 D5 0 D4 10 Month D3 Month.3 D2 Month.2 D1 Month.1 D0 Month.0 Contains the BCD digits for the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12. Batterybacked, read/write. 06h Timekeeping - Date of the month D7 0 D6 0 D5 10 date.1 D4 10 date.0 D3 Date.3 D2 Date.2 D1 Date.1 D0 Date.0 Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Battery-backed, read/write. 05h Timekeeping - Day of the week D7 0 D6 0 D5 0 D4 0 D3 0 D2 Day.2 D1 Day.1 D0 Day.0 Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date. Battery-backed, read/write. 04h Timekeeping - Hours D7 0 D6 0 D5 10 hours.1 D4 10 hours.0 D3 Hours.3 D2 Hours2 D1 Hours.1 D0 Hours.0 Contains the BCD value of hours in 24-hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23. Battery-backed, read/write. 03h Timekeeping - Minutes D7 0 D6 10 min.2 D5 10 min.1 D4 10 min.0 D3 Min.3 D2 Min.2 D1 Min.1 D0 Min.0 Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write. 02h Timekeeping - Seconds D7 0 D6 10 sec.2 D5 10 sec.1 D4 10 sec.0 D3 Seconds.3 D2 Seconds.2 D1 Seconds.1 D0 Seconds.0 Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write. Rev. 3.2 July 2010 Page 13 of 25 FM3104/16/64/256 01h CAL/Control D7 OSCEN D6 Reserved D5 CALS D4 CAL.4 D3 CAL.3 D2 CAL.2 D1 CAL.1 D0 CAL.0 /OSCEN Reserved CALS CAL.4-0 /Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator can save battery power during storage. On a power-up without battery, this bit is set to 1. Batterybacked, read/write. Reserved bits. Do not use. Should remain set to 0. Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. Calibration is explained on page 7. Nonvolatile, read/write. These five bits control the calibration of the clock. Nonvolatile, read/write. 00h Flags/Control D7 Reserved D6 CF D5 Reserved D4 Reserved D3 Reserved D2 CAL D1 W D0 R CF CAL W R Reserved Century Overflow Flag. This bit is set to a 1 when the values in the years register overflows from 99 to 00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new century information as needed. This bit is cleared to 0 when the Flag register is read. It is read-only for the user. Battery-backed. Calibration Mode. When set to 1, the clock enters calibration mode. When CAL is set to 0, the clock operates normally, and the CAL/PFO pin is controlled by the power fail comparator. Battery-backed, read/write. Write Time. Setting the W bit to 1 freezes the clock. The user can then write the timekeeping registers with updated values. Resetting the W bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters and restarts the clock. Battery-backed, read/write. Read Time. Setting the R bit to 1 copies a static image of the timekeeping core and place it into the user registers. The user can then read them without concerns over changing values causing system errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. Battery-backed, read/write. Reserved bits. Do not use. Should remain set to 0. Rev. 3.2 July 2010 Page 14 of 25 FM3104/16/64/256 Two-wire Interface The FM31xx employs an industry standard two-wire bus that is familiar to many users. This product is unique since it incorporates two logical devices in one chip. Each logical device can be accessed individually. Although monolithic, it appears to the system software to be two separate products. One is a memory device. It has a Slave Address (Slave ID = 1010b) that operates the same as a stand-alone memory device. The second device is a real-time clock and processor companion which have a unique Slave Address (Slave ID = 1101b). By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM31xx is always a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions: Start, Stop, Data bit, and Acknowledge. The figure below illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the Electrical Specifications section. SCL SDA Stop (Master) Start (Master) 7 6 0 Data bit Acknowledge (Transmitter) (Receiver) Data bits (Transmitter) Figure 9. Data Transfer Protocol Start Condition A Start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All read and write transactions begin with a Start condition. An operation in progress can be aborted by asserting a Start condition at any time. Aborting an operation using the Start condition will ready the FM31xx for a new operation. If the power supply drops below the specified VTP during operation, any 2-wire transaction in progress will be aborted and the system must issue a Start condition prior to performing another operation. Stop Condition A Stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations must end with a Stop condition. If an operation is pending when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition. Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high. Acknowledge The Acknowledge (ACK) takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter must release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a No-Acknowledge (NACK) and the operation is aborted. The receiver might NACK for two distinct reasons. First is that a byte transfer fails. In this case, the NACK ends the current operation so that the part can be addressed again. This allows the last byte to be recovered in the event of a communication error. Second and most common, the receiver does not send an ACK to deliberately terminate an operation. For example, during a read operation, the FM31xx will continue to place data onto the bus as long as the receiver sends ACKs (and clocks). When a read operation is complete and no more data is needed, the receiver must NACK the last byte. If the receiver ACKs the last byte, this will cause the FM31xx to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop. Rev. 3.2 July 2010 Page 15 of 25 FM3104/16/64/256 Slave Address The first byte that the FM31xx expects after a Start condition is the slave address. As shown in figures below, the slave address contains the Slave ID, Device Select address, and a bit that specifies if the transaction is a read or a write. The FM31xx has two Slave Addresses (Slave IDs) associated with two logical devices. To access the memory device, bits 7-4 should be set to 1010b. The other logical device within the FM31xx is the realtime clock and companion. To access this device, bits 7-4 of the slave address should be set to 1101b. A bus transaction with this slave address will not affect the memory in any way. The figures below illustrate the two Slave Addresses. The Device Select bits allow multiple devices of the same type to reside on the 2-wire bus. The device select bits (bits 2-1) select one of four parts on a twowire bus. They must match the corresponding value on the external address pins in order to select the device. Bit 0 is the read/write bit. A "1" indicates a read operation, and a "0" indicates a write operation. Slave ID Device Select Following the MSB is the LSB (lower byte) which contains the remaining eight address bits. The address is latched internally. Each access causes the latched address to be incremented automatically. The current address is the value that is held in the latch, either a newly written value or the address following the last access. The current address will be held as long as VDD > VTP or until a new value is written. Accesses to the clock do not affect the current memory address. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the Acknowledge, the FM31xx increments the internal address. This allows the next sequential byte to be accessed with no additional addressing externally. After the last address is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Addressing Overview - RTC & Companion The RTC and Processor Companion operate in a similar manner to the memory, except that it uses only one byte of address. Addresses 00h to 18h correspond to special function registers. Attempting to load addresses above 18h is an illegal condition; the FM31xx will return a NACK and abort the 2wire transaction. Data Transfer After the address information has been transmitted, data transfer between the bus master and the FM31xx begins. For a read, the FM31xx will place 8 data bits on the bus then wait for an ACK from the master. If the ACK occurs, the FM31xx will transfer the next byte. If the ACK is not sent, the FM31xx will end the read operation. For a write operation, the FM31xx will accept 8 data bits from the master then send an Acknowledge. All data transfer occurs MSB (most significant bit) first. Memory Write Operation All memory writes begin with a Slave Address, then a memory address. The bus master indicates a write operation by setting the slave address LSB to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an Acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap to 0000h. Internally, the actual memory write occurs after the 8th data bit is transferred. It will be complete before the Acknowledge is sent. Therefore, if the 1 7 0 6 1 5 0 4 X 3 A1 2 A0 1 R/W 0 Figure 10. Slave Address - Memory Slave ID Device Select 1 7 1 6 0 5 1 4 X 3 A1 2 A0 1 R/W 0 Figure 11. Slave Address - Companion Addressing Overview - Memory After the FM31xx acknowledges the Slave Address, the master can place the memory address on the bus for a write operation. The address requires two bytes. This is true for all members of the family. Therefore the 4Kb and 16Kb configurations will be addressed differently from stand alone serial memories but the entire family will be upwardly compatible with no software changes. The first is the MSB (upper byte). For a given density unused address bits are don't cares, but should be set to 0 to maintain upward compatibility. Rev. 3.2 July 2010 Page 16 of 25 FM3104/16/64/256 user desires to abort a write without altering the memory contents, this should be done using a Start or Stop condition prior to the 8th data bit. The figures below illustrate a single- and multiple-writes to memory. By Master Start Address & Data Stop S Slave Address 0A Address MSB A Address LSB A Data Byte A P By FM31xxx Acknowledge Figure 12. Single Byte Memory Write Start By Master S Slave Address 0A Address & Data Stop Address MSB A Address LSB A Data Byte A Data Byte A P By FM31xxx Acknowledge Figure 13. Multiple Byte Memory Write Each time the bus master acknowledges a byte, this indicates that the FM31xx should read out the next sequential byte. There are four ways to terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM31xx attempts to read out additional data onto the bus. The four valid methods follow. 1. The bus master issues a NACK in the 9th clock cycle and a Stop in the 10th clock cycle. This is illustrated in the diagrams below and is preferred. The bus master issues a NACK in the 9th clock cycle and a Start in the 10th. The bus master issues a Stop in the 9th clock cycle. The bus master issues a Start in the 9th clock cycle. Memory Read Operation There are two types of memory read operations. They are current address read and selective address read. In a current address read, the FM31xx uses the internal address latch to supply the address. In a selective read, the user performs a procedure to first set the address to a specific value. Current Address & Sequential Read As mentioned above the FM31xx uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to 1. This indicates that a read operation is requested. After receiving the complete device address, the FM31xx will begin shifting data out from the current address on the next clock. The current address is the value held in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. 2. 3. 4. If the internal address reaches the top of memory, it will wrap around to 0000h on the next read cycle. The figures below show the proper operation for current address reads. Selective (Random) Read There is a simple technique that allows a user to select a random address location as the starting point for a read operation. This involves using the first Rev. 3.2 July 2010 Page 17 of 25 FM3104/16/64/256 three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM31xx acknowledges the address, the bus master issues a Start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a 1. The operation is now a read from the current address. Read operations are illustrated below. RTC/Companion Write Operation All RTC and Companion writes operate in a similar manner to memory writes. The distinction is that a different device ID is used and only one byte address is needed instead of two. Figure 16 illustrates a single byte write to this device. RTC/Companion Read Operation As with writes, a read operation begins with the Slave Address. To perform a register read, the bus master supplies a Slave Address with the LSB set to 1. This indicates that a read operation is requested. After receiving the complete Slave Address, the FM31xx will begin shifting data out from the current register address on the next clock. Auto-increment operates for the special function registers as with the memory address. A current address read for the registers look exactly like the memory except that the device ID is different. The FM31xx contains two separate address registers, one for the memory address and the other for the register address. This allows the contents of one address register to be modified without affecting the current address of the other register. For example, this would allow an interrupted read to the memory while still providing fast access to an RTC register. A subsequent memory read will then continue from the memory address where it previously left off, without requiring the load of a new memory address. However, a write sequence always requires an address to be supplied. By Master Start Address No Acknowledge Stop S Slave Address 1A Data Byte 1 P By FM31xxx Acknowledge Data Figure 14. Current Address Memory Read By Master Start Address Acknowledge No Acknowledge Stop S Slave Address 1A Data Byte A Data Byte 1P By FM31xxx Acknowledge Data Figure 15. Sequential Memory Read Rev. 3.2 July 2010 Page 18 of 25 FM3104/16/64/256 Start By Master S Slave Address 0A Address Start Address No Acknowledge Stop Address MSB A Address LSB A S Slave Address 1A Data Byte 1P By FM31xxx Acknowledge Data Figure 16. Selective (Random) Memory Read By Master Start Address & Data Stop S Slave Address 0A000 Address A Data Byte A P By FM31xx Acknowledge Figure 17. Byte Register Write 2- Although not required, it is recommended that A5-A7 in the Register Address byte are zeros in order to preserve compatibility with future devices. Addressing FRAM Array in the FM31xx Family The FM31xx family includes 256Kb, 64Kb, 16Kb, and 4Kb memory densities. The following 2-byte address field is shown for each density. Table 4. Two-Byte Memory Address Part # 1st Address Byte FM31256 FM3164 FM3116 FM3104 x x x x A14 x x x A13 x x x A12 A12 x x A11 A11 x x A10 A10 A10 x A9 A9 A9 x A8 A8 A8 A8 A7 A7 A7 A7 A6 A6 A6 A6 2nd Address Byte A5 A5 A5 A5 A4 A4 A4 A4 A3 A3 A3 A3 A2 A2 A2 A2 A1 A1 A1 A1 A0 A0 A0 A0 Rev. 3.2 July 2010 Page 19 of 25 FM3104/16/64/256 Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any signal pin with respect to VSS VBAK TSTG TLEAD VESD Backup Supply Voltage Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) Ratings -1.0V to +7.0V -1.0V to +7.0V * and VIN VDD+1.0V ** -1.0V to +4.5V -55C to + 125C 260 C 4kV 1kV 250V Package Moisture Sensitivity Level MSL-1 * PFI input voltage must not exceed 4.5V. ** The "VIN < VDD+1.0V" restriction does not apply to the SCL and SDA inputs which do not employ a diode to VDD. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max VDD Main Power Supply 2.7 5.5 IDD VDD Supply Current @ SCL = 100 kHz 500 900 @ SCL = 400 kHz @ SCL = 1 MHz 1500 ISB Standby Current 150 For VDD < 5.5V 120 For VDD < 3.6V VBAK RTC Backup Supply Voltage 2.0 3.0 3.75 IBAK RTC Backup Supply Current 1 IBAKTC Trickle Charge Current 5 25 VTP0 VDD Trip Point Voltage, VTP(1:0) = 00b 2.55 2.6 2.70 VTP1 VDD Trip Point Voltage, VTP(1:0) = 01b 2.85 2.9 3.00 VTP2 VDD Trip Point Voltage, VTP(1:0) = 10b 3.80 3.9 4.00 VTP3 VDD Trip Point Voltage, VTP(1:0) = 11b 4.25 4.4 4.50 VRST VDD for valid /RST @ IOL = 80 A at VOL 0 VBAK > VBAK min 1.6 VBAK < VBAK min ILI Input Leakage Current 1 ILO Output Leakage Current 1 VIL Input Low Voltage 0.3 VDD -0.3 All inputs except those listed below -0.3 CNT1-2 battery backed (VDD < 2.5V) 0.5 -0.3 CNT1-2 (VDD > 2.5V) 0.8 VIH Input High Voltage 0.7 VDD VDD + 0.3 All inputs except those listed below PFI (comparator input) 3.75 CNT1-2 battery backed (VDD < 2.5V) VBAK - 0.5 VBAK + 0.3 CNT1-2 VDD > 2.5V 0.7 VDD VDD + 0.3 VOL Output Low Voltage (IOL = 3 mA) 0.4 VOH Output High Voltage (IOH = -2 mA) 2.4 RRST Pull-up Resistance for /RST Inactive 50 400 Continued Units V A A A A A V A A V V V V V V A A V V V V V V V V V K Notes 7 1 2 9 4 10 5 5 5 5 6 3 3 8 Rev. 3.2 July 2010 Page 20 of 25 FM3104/16/64/256 DC Operating Conditions, continued (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units RIN Input Resistance (pulldown) 20 A1-A0 for VIN = VIL max K 1 A1-A0 for VIN = VIH min M VPFI Power Fail Input Reference Voltage 1.175 1.20 1.225 V VHYS Power Fail Input (PFI) Hysteresis (Rising) 100 mV Notes Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. All inputs at VSS or VDD, static. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to A0, A1, PFI, or /RST pins. 4. VBAK = 3.0V, VDD < 2.4V, oscillator running, CNT1-2 at VBAK. 5. /RST is asserted low when VDD < VTP. 6. The minimum VDD to guarantee the level of /RST remains a valid VOL level. 7. Full complete operation. Supervisory circuits, RTC, etc operate to lower voltages as specified. 8. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM31xx. 9. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 10. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max. AC Parameters (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max fSCL SCL Clock Frequency 0 100 0 400 0 1000 tLOW Clock Low Period 4.7 1.3 0.6 tHIGH Clock High Period 4.0 0.6 0.4 tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tSP Bus Free Before New Transmission Start Condition Hold Time Start Condition Setup for Repeated Start Data In Hold Time Data In Setup Time Input Rise Time Input Fall Time Stop Condition Setup Time Data Output Hold (from SCL @ VIL) Noise Suppression Time Constant on SCL, SDA 4.7 4.0 4.7 0 250 1000 300 4.0 0 50 0.6 0 50 1.3 0.6 0.6 0 100 300 300 0.25 0 50 0.5 0.25 0.25 0 100 300 100 Units kHz s s s s s s ns ns ns ns s ns ns Notes 1 1 All SCL specifications as well as start and stop conditions apply to both read and write operations. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.0V) Symbol Parameter CIO Input/Output Capacitance CXTAL X1, X2 Crystal pin Capacitance Notes 1 This parameter is characterized but not tested. The crystal attached to the X1/X2 pins must be rated as 6pF. 2 Typ 12 Max 8 - Units pF pF Notes 1 1, 2 Data Retention (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V) Parameter Data Retention Min 10 Units Years Notes Rev. 3.2 July 2010 Page 21 of 25 FM3104/16/64/256 Supervisor Timing (TA = -40 C to + 85 C, VDD = 2.7V to 5.5V) Symbol Parameter tRPU /RST Active (low) after VDD>VTP tRNR VDD < VTP noise immunity tVR VDD Rise Time tVF VDD Fall Time tWDP Pulse Width of /RST for Watchdog Reset tWDOG Timeout of Watchdog fCNT Frequency of Event Counters Notes This parameter is characterized but not tested. 1 Slope measured at any point on VDD waveform. 2 tDOG is the programmed time in register 0Ah, VDD > VTP and tRPU satisfied. 3 Min 100 10 50 100 100 tDOG 0 Max 200 25 200 2*tDOG 10 Units ms s s/V s/V ms ms MHz Notes 1 1,2 1,2 3 /RST Timing VDD VTP VRST t RNR t RPU RST Rev. 3.2 July 2010 Page 22 of 25 FM3104/16/64/256 AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels 0.1 VDD to 0.9 VDD 10 ns 0.5 VDD Equivalent AC Load Circuit 5.5V 1700 Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tR Output 100 pF SCL t SU:STA tBUF tF t HIGH t LOW t SP t SP 1/fSCL SDA Start Stop Start tAA t DH t HD:DAT t SU:DAT Acknowledge Write Bus Timing tHD:DAT SCL tSU:STO tHD:STA tSU:DAT tAA SDA Start Stop Start Acknowledge Rev. 3.2 July 2010 Page 23 of 25 FM3104/16/64/256 Mechanical Drawing 14-pin SOIC (JEDEC Standard MS-012 variation AB) Recommended PCB Footprint ... 7.70 6.00 0.20 3.90 0.13 2.00 1.27 ... 3.70 0.65 Pin 1 8.64 0.10 1.35 1.75 0.25 0.50 45 0.19 0.25 1.27 0.33 0.51 0.10 0.25 0.10 mm 0- 8 0.40 1.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme Legend: XXXX= part number, P= package type (G="Green"/RoHS) LLLLLLL= lot code RIC=Ramtron Int'l Corp, YY=year, WW=work week Example: FM31256, "Green" SOIC package, Year 2009, Work Week 42 FM31256-G B90007G1 RIC 0942 XXXXXXX-P LLLLLLL RIC YYWW Rev. 3.2 July 2010 Page 24 of 25 FM3104/16/64/256 Revision History Revision 0.2 0.21 1.0 1.0a 2.0 Date 5/22/03 11/25/03 3/30/04 4/27/04 10/25/04 Summary Initial release. Fixed package drawing dimensions. Changed product status to Preliminary. Added VTP and VPFI parameters in DC Operating table. Changed VHYS limits. Added "green" package. Changed VPFI limits, changed VTF and VTR conditions and measurement units, created additional ISB specification, and added board layout section. Changed to Pre-Production status. Added text to Trickle Charger section. Improved spec limits on VTP, VPFI, and VHYS parameters and changed VIH max limits in DC Operating table. Added companion register table with default values. Added Package Marking Scheme and board footprint. Devices marked with Date Codes 0440 and higher comply with the revision of the datasheet. Changed description of POR flag and manual reset (pg. 5, 13). Added notes to Absolute Maximum Ratings. Rewrote section on battery backup. Added comment about unused CNT pins. Removed -S packaging option which is Not Recommended for New Designs. Added ESD and MSL ratings which are valid for Date Codes 0440 and higher. Not recommended for new designs. As an alternative, use FM3127xB for 5V designs or FM31L27xB for 3V designs. Changed to Production status. These products are no longer Not Recommended for New Designs (NRND). Updated ESD ratings. Updated lead temperature rating in Abs Max table. Removed battery insertion sequence text (p. 7). The sequence is no longer necessary for devices with date codes after 0701. Removed text indicating that a manual reset sets the POR flag. 2.1 2.2 2.3 2.4 3.0 3.1 3.2 12/8/04 11/2/05 10/2/06 2/6/2008 2/16/2010 3/23/2010 7/27/2010 Rev. 3.2 July 2010 Page 25 of 25 |
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